1. Field of the Invention
This invention relates to a method of producing a semiconductor device. More particularly, it relates to a method of producing a semiconductor device in which an impurity at a high concentration contained locally within a polycrystalline silicon film or the like is diffused in a lateral direction (a plane direction) by irradiation with a laser beam, whereby a MIS-FET (metal-insulator-semiconductor field effect transistor) of high breakdown voltage, a resistor, etc. can be formed at a high precision.
2. Description of the Prior Art
As is well known, a MIS-FET is such that a gate electrode is disposed on a semiconductor substrate through an insulating film which is made of, for example, silicon dioxide or silicon nitride and that a channel current to flow across a source and a drain is controlled by applying a voltage to the gate electrode.
In order to enhance the source-drain breakdown voltage of such MIS-FET, there has been proposed a MIS-FET called the offset gate type.
FIG. 1 is a view showing an example of the sectional structure of the offset gate type MIS-FET. This MIS-FET is the same as a conventional n-channel MIS-FET in that a source 2 and a drain 3 having a high n-type impurity concentration are disposed in surface regions of a p-type silicon substrate 1 and that a gate electrode 5 is disposed on the substrate 1 through an insulating film 4. An offset exists between the gate 5 and the drain 3, and an n-type low impurity concentration region 6 for moderating the electric field intensity betwen the gate 5 and the drain 3 so as to enhance the breakdown voltage between the source 2 and the drain 3 is formed.
For the gate electrode of the MIS-FET, a conductive metal such as aluminum was generally employed at first. At present, however, a polycrystalline silicon film has been often employed in order to raise the density of integration by self-alignment.
The offset gate type MIS-FET which employs the polycrystalline silicon film as the gate electrode is formed as follows.
As shown in FIG. 2, an insulating film 4 and a gate 5 are formed on a silicon substrate 1. Thereafter, using the gate 5 as a mask, ions of an n-type impurity are implanted to form an n-type low concentration region 6. Further, using a mask 7 made of an SiO.sub.2 film or the like, a large quantity of n-type impurity is implanted by the ion implantation, to form a source 2 and a drain 3.
As apparent from FIG. 1, in the offset gate type MIS-FET, the left end and right end of the gate 5 must be in perfect alignment with the right end of the source 2 and the left end of the low concentration region 6 respectively. When it is intended to realize such structure by the prior-art method described above, a part of the gate 5 becomes a high resistance, which has led to the problem that the switching characteristics of the MIS-FET degrade conspicuously.
More specifically, the mask 7 is formed by the well-known photoetching. The photoetching inevitably involves some degree of error of registration. It is therefore impossible to perfectly align the right end of the gate 5 with the left end of the mask 7.
If a gap appears between the right end of the gate 5 and the left end of the mask 7, a large quantity of impurity is implanted also underneath the gap by the ion implantation at a high concentration to be subsequently carried out, and the formation of the offset gate type MIS-FET becomes impossible.
In order to prevent the formation of such gap, the mask 7 for the ion implantation is formed so that the gate 5 and the mask 7 may overlap each other as illustrated in FIG. 2.
Thus, it is tentatively possible to form the offset gate type MIS-FET. However, no ion is implanted into the region of the gate 5 covered with the mask, and the ions are implanted into only the exposed region.
In consequence, the whole gate 5 does not become a low resistance, but a low resistance region 8 of high impurity concentration and a high resistance region 9 of low impurity concentration are formed.
When the high resistance region 9 exists in the gate electrode 5, the switching characteristics of the MIS-FET are limited by the resistance of this portion and worsen conspicuously.
In order to solve such problem, the impurity contained in the high concentration region 8 may be diffused in the lateral direction so as to distribute the impurity uniformly in the whole gate 5, or alternatively, a large quantity of impurity may be contained in advance within the polycrystalline silicon making up the gate electrode 5.
Heretofore, however, for the lateral diffusion of the impurity there has not been any other method than heating the entire silicon substrate to a high temperature, and it has been extremely difficult to laterally diffuse the impurity without degrading other characteristics. The measure in which a large quantity of impurity is contained within the polycrystalline silicon in advance has incurred the problems of a remarkable increase in the number of required process steps and a low workability of the polycrystalline silicon of high impurity concentration. Both the measures have been difficult to be put into practical use.
For the sake of convenience, the case of the offset gate type MIS-FET has been exemplified. It is obvious, however, that if an impurity can be diffused in the lateral direction without exerting any influence on others, this is very useful for the production of various semiconductor devices including, not only the offset type MIS-FET, but also diodes, resistors etc.
Nevertheless, it has not hitherto been carried out at all that an impurity of high concentration existing locally is diffused in the lateral direction so as to form a uniform layer of low resistance.